The present invention relates to microelectronic substrates such as multi-layer circuit panels. Multi-layer circuit panels are used throughout the microelectronic arts for purposes such as mounting and interconnecting other components. For example, multiple semiconductor chips can be mounted to a single circuit panel and contacts on the various chips may be interconnected with one another by electrically conductive features of the circuit panel. Typically, the circuit panels are regarded as having xe2x80x9chorizontalxe2x80x9d directions, also referred to as the xe2x80x9cxxe2x80x9d and xe2x80x9cyxe2x80x9d directions parallel to the exposed component and mounting surfaces of the panels. Such circuit panels typically include several dielectric layers such as unreinforced or reinforced epoxy, polyimide or the like. The circuit panels also include electrically conductive features such as elongated electrical conductors commonly referred to as xe2x80x9ctracesxe2x80x9d extending along surfaces of the dielectric layers, so that each layer of traces is disposed at the juncture between a pair of adjacent dielectric layers or else is disposed on an exposed surface, at the top or bottom of the stack. One widely used arrangement has many of the traces within each layer extending generally parallel to one another. Thus, the majority of traces in one layer may extend in the first or x horizontal direction, whereas the majority of traces in another layer may extend in a perpendicular or y horizontal direction. The various traces can be interconnected with one another by vertical conductors or xe2x80x9cviasxe2x80x9d extending in the vertical or z-direction. As described, for example, in commonly assigned U.S. Pat. Nos. 5,367,764 and 5,282,312, the disclosures of which are hereby incorporated by reference herein, vertical or z-direction connectors may be provided in various locations within such a multi-layer circuit panel so as to provide the desired pattern of connections within the traces of the various layers. Such pattern may include complex conductive paths extending along traces of various layers and extending between the layers along the vias.
Typically, the various dielectric layers, with the traces thereon and with vias extending through each individual layer are laminated together so as to form the composite, multi-layer structure. Various techniques are used to provide vertical conductors or vias extending through a plurality of dielectric layers. For example, special connecting layers may be formed from a dielectric material with adhesives or bonding agents on opposite sides of the connecting layer. The connecting layers are provided with vias extending through them. These vias may have electrically conductive bonding materials on their exposed surfaces. The connecting layers are placed into the laminate when the various layers are laminated to one another. The vias of the connecting layers can connect features on the adjacent layers to one another. Systems of this type, however, generally require care in assembly so as to assure reliable interconnections. In particular, because the adhesives on the connecting layers are activated at the same time as the conductive bonding materials used to make the electrical connections, the adhesives can be introduced into the electrical connections and can interfere with reliable connections. Although solutions to this problem are disclosed in the aforementioned ""367 and ""312 patents, it would be desirable to provide additional methods of interconnection which avoid the need for such solutions.
Moreover, vias of this type consume significant space within the assembly. Typically, the conductive vias in the connecting layers have flanges with diameters on the order of 0.010 inches, i.e., about 250 micrometers. The flanges engage corresponding flanges on the mating surface of the next dielectric layer in the stack. The area occupied by the flanges must remain free of traces. Moreover, the areas immediately adjacent the flanges on the mating surface must also remain free of traces to avoid accidental short circuiting due to misalignment between the layers. The space consumed by vertical connections made by using vias and connecting layers substantially reduces the number of traces which can be provided on the surfaces of the dielectric layers. Stated another way, the ability of the panel to provide routing between the various electrical components to be connected is diminished.
In another method, the structure can be drilled after laminating the layers so as to form a vertical hole extending at least partially through the assembly. After drilling, a conductive material is deposited into the holes to form vertical connections between layers. The drilling procedure suffers from numerous drawbacks, including significant loss of space within the assembly. To form a vertical connection between two layers in the middle of the laminate, a hole must be drilled from an exposed surface of the laminate through all of the overlying layers so as to reach the layers to be connected. The layout of traces on all of the overlying layers must be arranged to provide clearance for such a hole and to accommodate the tolerances inherent in the hole drilling procedure. Moreover, the hole drilling procedure is expensive and slow. Consequently, the hole drilling procedure often is used to provide only a few connections as, for example, ground or power connections between layers.
All of the foregoing problems are becoming progressively more acute as the trend towards smaller circuit panels, with finer traces continues.
One aspect of the invention provides a multilayer microelectronic component. A component according to this aspect of the invention includes first and second substrates. Each such substrate includes at least one dielectric layer and electrically conductive features such as traces extending in one or more horizontal directions along the at least one dielectric layer; electrically conductive potential planes extending in horizontal directions along the at least one dielectric layer, or both. The component further includes a first intermediate dielectric layer disposed between the first and second substrates. A first set of elongated, electrically conductive leads extends through the first intermediate layer. Some or all of these leads are electrically connected between conductive features of the first and second substrates. As further discussed below, such leads can provide compact interconnections which leave substantial room for routing traces on the surfaces of the substrates. The vertical interconnect density (number of vertical interconnects per unit area) which can be provided in preferred structures according to this aspect of the invention may be several times greater than the interconnect density which can be provided using conventional via-bearing intermediate layers.
The properties of the intermediate layer can be controlled to provide either a rigid interconnection or a compliant connection which allows relative movement of the substrates. The substrates may have different coefficients of thermal expansion. For example, one substrate may be a conventional polymer-and-copper circuit panel, whereas the other substrate may be formed from silicon or a material having a coefficient of thermal expansion closely matched to silicon. A silicon chip or chips can be rigidly mounted to the expansion-matched substrate.
A further aspect of the invention provides methods of making these and other components. A method according to this aspect of the invention may include the steps of providing a first substrate and a second substrate, each such substrate including at least one dielectric layer and electrically conductive features as aforesaid, and providing a first set of elongated, vertically-extensive leads extending at least partially between the first and second substrates, the leads being electrically connected between the electrically conductive features on the first and second substrates. The method desirably further includes injecting a flowable material around the leads and curing said flowable material to form a first intermediate layer, desirably a dielectric layer, between the substrates. The cured intermediate layer intimately surrounds and encapsulates the first set of leads, and preferably seals against the adjoining surfaces of the substrates.
Because the electrical connections have been made before the flowable material is applied, the flowable material cannot interfere with the electrical connections. Preferably, the step of providing the first set of said vertically-extensive leads includes connecting these leads between the substrates while these leads are in a horizontal disposition and moving the substrates away from one another so as to bend said leads to a vertically extensive disposition. Such a process makes numerous connections simultaneously and reliably, at low cost.
The leads may be formed by connecting partial leads carried by opposing substrates to one another. The leads may include sections, such as the connected partial leads, extending transverse to one another. As further explained below, the partial leads provided on each substrate may be generally aligned with the predominant direction of traces at or near the surface of such substrate bearing the leads. This faciliates placement of the leads and traces, and enhances routability, i.e., the ability of the substrate to accommodate trace routings.
Yet another aspect of the invention provides methods of making a multilayer structure while selectively providing vertical interconnections. Methods according to this aspect of the invention include providing a plurality of substrates and a first set of leads in a generally horizontal disposition on a surface of one of said substrates, each such lead having a fixed end permanently attached to one of said substrates and a free end movable with respect to such substrate. The leads are electrically connected between conductive features on different ones of said substrates by making bonds at free ends of the leads, as, for example, by bonding the free ends directly to the features on another substrate or by bonding the free ends to free ends of leads carried by the other substrate to form composite leads extending between the substrates. The substrates are the moved away from one another so as to deform the leads to a vertically-extensive disposition.
At least one of these steps is controlled so as to selectively control the connections between conductive features on different substrates provided by said leads. For example, the selective control may be provided by controlling the bond-making step, or by controlling the formation of connections between the lead fixed ends and conductive features on the substrate which initially carries the first set of leads. Also, the leads may be selectively provided or omitted. As further explained below, the steps required for selective control of the connections provided by the leads can be performed by treating, forming or removing features on the surface of the substrate. The process facilitates customization of the vertical interconnections.
In further processes according to other aspects of the invention, a component formed by joining two or more substrate layers in a process as aforesaid can be used as a substrate in a further repetition of the process so that the component is itself joined to another substrate. Also, the substrates may be of different sizes, so that a relatively small substrate may be joined to a larger circuit board or other substrate. The smaller substrate thus forms a xe2x80x9cpatchxe2x80x9d on the larger substrate. Such a process can be used, for example, to provide a localized high wiring density area. In further variant, one of the substrates may have leads disposed on an exterior surface which remains exposed after the substrates have been joined to one another. These leads may form an attachment to a chip or other microelectronic component. In one embodiment, such attachment can provide a compliant, strain-relieving connection between the chip and substrate.